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1. general description the 74lv4020 is a low-voltage si-gate cmos device and is pin and function compatible with the 74hc4020 and 74hct4020. the 74lv4020 is a 14-stage binary ripple counter with a clock input ( cp), an overriding asynchronous master reset input (mr) and 12 fully buffered parallel outputs (q0, and q3 to q13). the counter advances on the high-to-low transition of cp. a high on mr clears all counter stages and forces all outputs low, independent of the state of cp. each counter stage is a static toggle ?ip-?op. 2. features n optimized for low-voltage applications: 1.0 v to 5.5 v n accepts ttl input levels between v cc = 2.7 v and v cc = 3.6 v n typical low-level output voltage (peak) or output ground bounce: v ol(p) < 0.8 v at v cc = 3.3 v and t amb =25 c n typical high-level output voltage (valley) or output v oh undershoot: v oh(v) >2v at v cc = 3.3 v and t amb =25 c n esd protection: u hbm eia/jesd22-a114-c exceeds 2000 v u mm eia/jesd22-a115-a exceeds 200 v. n multiple package options n speci?ed from - 40 c to +80 c and from - 40 c to +125 c. 3. applications n frequency dividing circuits n time delay circuits n control counters 74lv4020 14-stage binary ripple counter rev. 01 29 november 2005 product data sheet
74lv4020_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 2 of 20 philips semiconductors 74lv4020 14-stage binary ripple counter 4. quick reference data [1] c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i n+ ? (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in v; n = number of inputs switching; ? (c l v cc 2 f o ) = sum of outputs. 5. ordering information table 1: quick reference data gnd = 0 v; t amb =25 c; t r =t f = 2.5 ns. symbol parameter conditions min typ max unit t phl , t plh propagation delay c l = 15 pf; v cc = 3.3 v cp to q0 - 12 - ns qn to q(n+1) - 7 - ns t phl propagation delay c l = 15 pf; v cc = 3.3 v mr to qn - 16 - ns f max maximum input clock frequency c l = 15 pf; v cc = 3.3 v - 100 - mhz c i input capacitance - 3.5 - pf c pd power dissipation capacitance per gate; v i = gnd to v cc [1] -20-pf table 2: ordering information type number package temperature range name description version 74lv4020n - 40 c to +125 c dip16 plastic dual in-line package; 16 leads (300 mil) sot38-4 74lv4020d - 40 c to +125 c so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 74lv4020db - 40 c to +125 c ssop16 plastic shrink small outline package; 16 leads; body width 5.3 mm sot338-1 74LV4020PW - 40 c to +125 c tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1
74lv4020_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 3 of 20 philips semiconductors 74lv4020 14-stage binary ripple counter 6. functional diagram fig 1. functional diagram fig 2. logic symbol fig 3. iec logic symbol 001aad722 14-stage counter 9 q0 7 q3 5 q4 4 q5 6 q6 13 q7 12 q8 14 q9 15 q10 1 q11 2 q12 3 q13 10 11 t c d mr cp 001aad723 q0 9 11 mr 10 cp q3 7 q4 5 q5 4 q6 6 q7 13 q8 12 q9 14 q10 15 q11 1 q12 2 q13 3 001aad724 09 11 ct + 10 ctr14 ct 7 5 4 6 13 12 14 15 1 2 13 3 fig 4. logic diagram 001aad725 cp mr ff 0 q t rd q0 q ff 2 q t rd q ff 7 q t rd q7 q ff 9 q t rd q9 q ff 1 q t rd q ff 8 q t rd q8 q ff 10 q t rd q10 q ff 11 q t rd q11 q ff 12 q t rd q12 q ff 13 q t rd q13 q ff 3 q t rd q3 q ff 4 q t rd q4 q ff 5 q t rd q5 q ff 6 q t rd q6 q
74lv4020_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 4 of 20 philips semiconductors 74lv4020 14-stage binary ripple counter 7. pinning information 7.1 pinning 7.2 pin description fig 5. pin con?guration dip16, so16, ssop16 and tssop16 4020 q11 v cc q12 q10 q13 q9 q5 q7 q4 q8 q6 mr q3 cp gnd q0 001aad721 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 table 3: pin description symbol pin description q11 1 parallel output 11 q12 2 parallel output 12 q13 3 parallel output 13 q5 4 parallel output 5 q4 5 parallel output 4 q6 6 parallel output 6 q3 7 parallel output 3 gnd 8 ground (0 v) q0 9 parallel output 0 cp 10 clock input (high-to-low, edge-triggered) mr 11 master reset input (active high) q8 12 parallel output 8 q7 13 parallel output 7 q9 14 parallel output 9 q10 15 parallel output 10 v cc 16 supply voltage
74lv4020_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 5 of 20 philips semiconductors 74lv4020 14-stage binary ripple counter 8. functional description 8.1 function table [1] h = high voltage level; l = low voltage level; x = dont care; - = low-to-high clock transition; = high-to-low clock transition. 8.1.1 timing diagram table 4: function table [1] input output cp mr q0, q3 to q13 - l no change l count xhl fig 6. timing diagram 001aad726 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 cp input mr input q0 q3 q4 q5 q6 q7 q8 q9 q10 q11 8192 16384 q12 q13
74lv4020_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 6 of 20 philips semiconductors 74lv4020 14-stage binary ripple counter 9. limiting values [1] above t amb = 70 c: p tot derates linearly with 12 mw/k. [2] above t amb = 70 c: p tot derates linearly with 8 mw/k. [3] above t amb = 60 c: p tot derates linearly with 5.5 mw/k. 10. recommended operating conditions [1] the static characteristics are guaranteed from v cc = 1.2 v to v cc = 5.5 v, but lv devices are guaranteed to function down to v cc = 1.0 v (with input levels gnd or v cc ). table 5: limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage - 0.5 +7 v i ik input clamping current v i < - 0.5 v or v i > v cc + 0.5 v - 20 ma i ok output clamping current v o < - 0.5 v or v o >v cc + 0.5 v - 50 ma i o output current v o = - 0.5 v to v cc + 0.5 v - 25 ma i cc quiescent supply current - 50 ma i gnd ground current - - 50 ma t stg storage temperature - 65 +150 c p tot total power dissipation t amb = - 40 c to +125 c dip16 package [1] - 750 mw so16 package [2] - 500 mw ssop16 and tssop16 packages [3] - 400 mw table 6: recommended operating conditions symbol parameter conditions min typ max unit v cc supply voltage [1] 1.0 3.3 5.5 v v i input voltage 0 - v cc v v o output voltage 0 - v cc v t amb ambient temperature - 40 - +125 c d t/ d v input transition rise and fall rate v cc = 1.0 v to 2.0 v - - 500 ns/v v cc = 2.0 v to 2.7 v - - 200 ns/v v cc = 2.7 v to 3.6 v - - 100 ns/v v cc = 3.6 v to 5.5 v - - 50 ns/v
74lv4020_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 7 of 20 philips semiconductors 74lv4020 14-stage binary ripple counter 11. static characteristics table 7: static characteristics at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit t amb = - 40 c to +85 c [1] v ih high-state input voltage v cc = 1.2 v 0.9 - - v v cc = 2.0 v 1.4 - - v v cc = 2.7 v to 3.6 v 2.0 - - v v cc = 4.5 v to 5.5 v 0.7 v cc -- v v il low-state input voltage v cc = 1.2 v - - 0.3 v v cc = 2.0 v - - 0.6 v v cc = 2.7 v to 3.6 v - - 0.8 v v cc = 4.5 v to 5.5 v - - 0.3 v cc v v oh high-state output voltage v i = v ih or v il i o = - 100 m a; v cc = 1.2 v - 1.2 - v i o = - 100 m a; v cc = 2.0 v 1.8 2.0 - v i o = - 100 m a; v cc = 2.7 v 2.5 2.7 - v i o = - 100 m a; v cc = 3.0 v 2.8 3.0 - v i o = - 100 m a; v cc = 4.5 v 4.3 4.5 - v i o = - 6 ma; v cc = 3.0 v 2.40 2.82 - v i o = - 12 ma; v cc = 4.5 v 3.60 4.20 - v v ol low-state output voltage v i = v ih or v il i o = 100 m a; v cc = 1.2 v - 0 - v i o = 100 m a; v cc = 2.0 v - 0 0.2 v i o = 100 m a; v cc = 2.7 v - 0 0.2 v i o = 100 m a; v cc = 3.0 v - 0 0.2 v i o = 100 m a; v cc = 4.5 v - 0 0.2 v i o = 6 ma; v cc = 3.0 v - 0.25 0.40 v i o = 12 ma; v cc = 4.5 v - 0.35 0.55 v i li input leakage current v i = v cc or gnd; v cc = 5.5 v - - 1.0 m a i cc quiescent supply current v i = v cc or gnd; i o = 0 a; v cc = 5.5 v - - 20.0 m a d i cc additional quiescent supply current per input; v i = v cc - 0.6 v; v cc = 2.7 v to 3.6 v - - 500 m a c i input capacitance - 3.5 - pf t amb = - 40 c to +125 c v ih high-state input voltage v cc = 1.2 v 0.9 - - v v cc = 2.0 v 1.4 - - v v cc = 2.7 v to 3.6 v 2.0 - - v v cc = 4.5 v to 5.5 v 0.7 v cc -- v
74lv4020_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 8 of 20 philips semiconductors 74lv4020 14-stage binary ripple counter [1] all typical values are measured at t amb = 25 c. v il low-state input voltage v cc = 1.2 v - - 0.3 v v cc = 2.0 v - - 0.6 v v cc = 2.7 v to 3.6 v - - 0.8 v v cc = 4.5 v to 5.5 v - - 0.3 v cc v v oh high-state output voltage v i = v ih or v il i o = - 100 m a; v cc = 1.2 v - - - v i o = - 100 m a; v cc = 2.0 v 1.8 - - v i o = - 100 m a; v cc = 2.7 v 2.5 - - v i o = - 100 m a; v cc = 3.0 v 2.8 - - v i o = - 100 m a; v cc = 4.5 v 4.3 - - v i o = - 6 ma; v cc = 3.0 v 2.20 - - v i o = - 12 ma; v cc = 4.5 v 3.50 - - v v ol low-state output voltage v i = v ih or v il i o = 100 m a; v cc = 1.2 v - - - v i o = 100 m a; v cc = 2.0 v - - 0.2 v i o = 100 m a; v cc = 2.7 v - - 0.2 v i o = 100 m a; v cc = 3.0 v - - 0.2 v i o = 100 m a; v cc = 4.5 v - - 0.2 v i o = 6 ma; v cc = 3.0 v - - 0.50 v i o = 12 ma; v cc = 4.5 v - - 0.65 v i li input leakage current v i = v cc or gnd; v cc = 5.5 v - - 1.0 m a i cc quiescent supply current v i = v cc or gnd; i o = 0 a; v cc = 5.5 v - - 160 m a d i cc additional quiescent supply current per input; v i = v cc - 0.6 v; v cc = 2.7 v to 3.6 v - - 850 m a table 7: static characteristics continued at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit
74lv4020_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 9 of 20 philips semiconductors 74lv4020 14-stage binary ripple counter 12. dynamic characteristics table 8: dynamic characteristics voltages are referenced to gnd (ground = 0 v); c l = 50 pf; for test circuit see figure 9 . symbol parameter conditions min typ max unit t amb = - 40 c to +85 c [1] t phl , t plh propagation delay cp to q0 see figure 7 v cc = 1.2 v - 60 - ns v cc = 2.0 v - 27 43 ns v cc = 2.7 v - 19 31 ns v cc = 3.0 v to 3.6 v - 16 26 ns v cc = 4.5 v to 5.5 v - 11 17 ns v cc = 3.3 v; c l = 15 pf - 12 - ns qn to q(n+1) see figure 7 v cc = 1.2 v - 40 - ns v cc = 2.0 v - 18 29 ns v cc = 2.7 v - 13 21 ns v cc = 3.0 v to 3.6 v - 11 18 ns v cc = 4.5 v to 5.5 v - 7 12 ns v cc = 3.3 v; c l = 15 pf - 7 - ns t phl propagation delay mr to qn see figure 8 v cc = 1.2 v - 55 - ns v cc = 2.0 v - 27 44 ns v cc = 2.7 v - 19 31 ns v cc = 3.0 v to 3.6 v - 16 26 ns v cc = 4.5 v to 5.5 v - 11 17 ns v cc = 3.3 v; c l = 15 pf - 16 - ns t w pulse width cp (high and low) see figure 7 v cc = 2.0 v 35 7 - ns v cc = 2.7 v 25 5 - ns v cc = 3.0 v to 3.6 v 20 4 - ns v cc = 4.5 v to 5.5 v 15 3 - ns mr (high) see figure 8 v cc = 2.0 v 35 11 - ns v cc = 2.7 v 25 9 - ns v cc = 3.0 v to 3.6 v 20 8 - ns v cc = 4.5 v to 5.5 v 15 7 - ns
74lv4020_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 10 of 20 philips semiconductors 74lv4020 14-stage binary ripple counter t rec recovery time mr to cp see figure 8 v cc = 1.2 v - 10 - ns v cc = 2.0 v 22 5 - ns v cc = 2.7 v 16 4 - ns v cc = 3.0 v to 3.6 v 13 3 - ns v cc = 4.5 v to 5.5 v 10 2 - ns f max maximum input clock frequency see figure 7 v cc = 2.0 v 14 60 - mhz v cc = 2.7 v 19 76 - mhz v cc = 3.0 v to 3.6 v 24 94 - mhz v cc = 4.5 v to 5.5 v 36 112 - mhz v cc = 3.3 v; c l = 15 pf - 100 - mhz c pd power dissipation capacitance per gate; v i = gnd to v cc [2] -20-pf t amb = - 40 c to +125 c t phl , t plh propagation delay cp to q0 see figure 7 v cc = 1.2v ---ns v cc = 2.0 v - - 54 ns v cc = 2.7 v - - 38 ns v cc = 3.0 v to 3.6 v - - 32 ns v cc = 4.5 v to 5.5 v - - 22 ns qn to q(n+1) see figure 7 v cc = 1.2v ---ns v cc = 2.0 v - - 37 ns v cc = 2.7 v - - 26 ns v cc = 3.0 v to 3.6 v - - 22 ns v cc = 4.5 v to 5.5 v - - 15 ns t phl propagation delay mr to qn see figure 8 v cc = 1.2v ---ns v cc = 2.0 v - - 55 ns v cc = 2.7 v - - 39 ns v cc = 3.0 v to 3.6 v - - 32 ns v cc = 4.5 v to 5.5 v - - 22 ns table 8: dynamic characteristics continued voltages are referenced to gnd (ground = 0 v); c l = 50 pf; for test circuit see figure 9 . symbol parameter conditions min typ max unit
74lv4020_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 11 of 20 philips semiconductors 74lv4020 14-stage binary ripple counter [1] typical values are measured at nominal v cc and t amb = 25 c. [2] c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i n+ s (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in v; n = number of inputs switching; s (c l v cc 2 f o ) = sum of the outputs. t w pulse width cp (high and low) see figure 7 v cc = 2.0 v 41 - - ns v cc = 2.7 v 30 - - ns v cc = 3.0 v to 3.6 v 24 - - ns v cc = 4.5 v to 5.5 v 18 - - ns mr (high) see figure 8 v cc = 2.0 v 41 - - ns v cc = 2.7 v 30 - - ns v cc = 3.0 v to 3.6 v 24 - - ns v cc = 4.5 v to 5.5 v 18 - - ns t rec recovery time mr to cp see figure 8 v cc = 1.2v ---ns v cc = 2.0 v 26 - - ns v cc = 2.7 v 19 - - ns v cc = 3.0 v to 3.6 v 15 - - ns v cc = 4.5 v to 5.5 v 12 - - ns f max maximum input clock frequency see figure 7 v cc = 2.0 v 12 - - mhz v cc = 2.7 v 16 - - mhz v cc = 3.0 v to 3.6 v 20 - - mhz v cc = 4.5 v to 5.5 v 30 - - mhz table 8: dynamic characteristics continued voltages are referenced to gnd (ground = 0 v); c l = 50 pf; for test circuit see figure 9 . symbol parameter conditions min typ max unit
74lv4020_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 12 of 20 philips semiconductors 74lv4020 14-stage binary ripple counter 13. waveforms measurement points: v m = 0.5 v cc . v ol and v oh are typical output voltage drop that occur with the output load. fig 7. propagation delay clock ( cp) to output (qn), clock pulse width and maximum clock frequency measurement points: v m = 0.5 v cc . v ol and v oh are typical output voltage drop that occur with the output load. fig 8. propagation delay master reset (mr) to output (qn), pulse width master reset (mr) and removal time master reset (mr) to clock ( cp) 001aad727 input cp, qn output q0, q(n+1) t phl t plh t w v oh v i gnd v ol v m v m 1/f max 001aad728 mr input cp input qn output t phl t w t rec v m v i gnd v i v oh v ol gnd v m v m
74lv4020_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 13 of 20 philips semiconductors 74lv4020 14-stage binary ripple counter test data is given in t ab le 9 . de?nitions for test circuit: r l = load resistor. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to output impedance z o of the pulse generator. fig 9. load circuitry for switching times table 9: test data supply voltage input load test v cc v i t r , t f c l r l 1.2 v v cc 2.5 ns 50 pf 1 k w t phl , t plh 2.0 v v cc 2.5 ns 50 pf 1 k w t phl , t plh 2.7 v 2.7 v 2.5 ns 50 pf 1 k w t phl , t plh 3.0 v to 3.6 v 2.7 v 2.5 ns 50 pf, 15 pf 1 k w t phl , t plh 4.5 v to 5.5 v v cc 2.5 ns 50 pf 1 k w t phl , t plh v cc v i v o 001aaa663 d.u.t. c l 50 pf r t r l 1 k w pulse generator
74lv4020_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 14 of 20 philips semiconductors 74lv4020 14-stage binary ripple counter 14. package outline fig 10. package outline sot38-1 (dip16) references outline version european projection issue date iec jedec jeita sot38-4 95-01-14 03-02-13 m h c (e ) 1 m e a l seating plane a 1 w m b 1 b 2 e d a 2 z 16 1 9 8 e pin 1 index b 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. unit a max. 12 b 1 (1) (1) (1) b 2 cd e e m z h l mm dimensions (inch dimensions are derived from the original mm dimensions) a min. a max. b max. w m e e 1 1.73 1.30 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 3.60 3.05 0.254 2.54 7.62 8.25 7.80 10.0 8.3 0.76 4.2 0.51 3.2 inches 0.068 0.051 0.021 0.015 0.014 0.009 1.25 0.85 0.049 0.033 0.77 0.73 0.26 0.24 0.14 0.12 0.01 0.1 0.3 0.32 0.31 0.39 0.33 0.03 0.17 0.02 0.13 dip16: plastic dual in-line package; 16 leads (300 mil) sot38-4
74lv4020_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 15 of 20 philips semiconductors 74lv4020 14-stage binary ripple counter fig 11. package outline sot109-1 (so16) x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot109-1 99-12-27 03-02-19 076e07 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1
74lv4020_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 16 of 20 philips semiconductors 74lv4020 14-stage binary ripple counter fig 12. package outline sot338-1 (ssop16) unit a 1 a 2 a 3 b p cd (1) e (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 1.25 7.9 7.6 1.03 0.63 0.9 0.7 1.00 0.55 8 0 o o 0.13 0.2 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. sot338-1 99-12-27 03-02-19 (1) w m b p d h e e z e c v m a x a y 1 8 16 9 q a a 1 a 2 l p q detail x l (a ) 3 mo-150 pin 1 index 0 2.5 5 mm scale ssop16: plastic shrink small outline package; 16 leads; body width 5.3 mm sot338-1 a max. 2
74lv4020_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 17 of 20 philips semiconductors 74lv4020 14-stage binary ripple counter fig 13. package outline sot403-1 (tssop16) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot403-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 18 16 9 q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 a max. 1.1 pin 1 index
74lv4020_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 18 of 20 philips semiconductors 74lv4020 14-stage binary ripple counter 15. abbreviations 16. revision history table 10: abbreviations acronym description cmos complementary metal oxide semiconductor ttl transistor transistor logic hbm human body model esd electrostatic discharge mm machine model table 11: revision history document id release date data sheet status change notice doc. number supersedes 74lv4020_1 20051129 product data sheet - - -
philips semiconductors 74lv4020 14-stage binary ripple counter 74lv4020_1 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 29 november 2005 19 of 20 17. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 18. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 19. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 20. trademarks notice all referenced brands, product names, service names and trademarks are the property of their respective owners. 21. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com level data sheet status [1] product status [2] [3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2005 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 29 november 2005 document number: 74lv4020_1 published in the netherlands philips semiconductors 74lv4020 14-stage binary ripple counter 22. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 ordering information . . . . . . . . . . . . . . . . . . . . . 2 6 functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 functional description . . . . . . . . . . . . . . . . . . . 5 8.1 function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8.1.1 timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 10 recommended operating conditions. . . . . . . . 6 11 static characteristics. . . . . . . . . . . . . . . . . . . . . 7 12 dynamic characteristics . . . . . . . . . . . . . . . . . . 9 13 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 17 data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19 18 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 20 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 21 contact information . . . . . . . . . . . . . . . . . . . . 19

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